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ADM1041
SMBus PROTOCOLS FOR RAM AND EEPROM
The ADM1041 contains volatile registers (RAM) and nonvola-
tile EEPROM. RAM occupies the address locations from 00h to
7Fh, while EEPROM occupies the address locations from 8000h
The EEPROM page address consists of the EEPROM address
high Byte 80h for FRU or 81h for register default and the three
MSBs of the low byte. The lower five bits of the EEPROM
address of the low byte are ignored during an erase operation.
to 813Fh.
The SMBus specification defines several protocols for different
1
S
2
SLAVE
ADDRESS
3
W A
4
COMMAND A2h
(PAGE ERASE)
5
A
6
EEPROM
ADDRESS
HIGH BYTE
(80h OR 81h)
7
A
8
EEPROM
ADDRESS
LOW BYTE
(00h TO FFh)
9
A
10
ARBITRARY
DATA
11 12
A P
types of read and write operations. The ones used in the
ADM1041 are discussed in the next sections. The following
abbreviations are used in the diagrams:
S—START
P—STOP
R—READ
W—WRITE
A—ACKNOWLEDGE
A—NO ACKNOWLEDGE
The ADM1041 uses the following SMBus write protocols.
SMBus Erase EEPROM Page Operations
EEPROM memory can be written to only if it is effectively
unprogrammed. Before writing to one or more locations that
are already programmed, the page containing those locations
must be erased. EEPROM ERASE is performed by sending a
page erase command byte (A2h) followed by the page location
of what you want to erase. (There is no need to set an erase bit
in an EEPROM control/status register.)
The EEPROM consists of 16 pages of 32 bytes each; the register
default EEPROM consists of 1 page of 32 bytes starting at 8100h.
Table 7. EEPROM Page Layout
Figure 28. EEPROM Page Erase Operation
Page erasure takes approximately 20 ms. If the EEPROM is
accessed before erasure is complete, the SMBus responds with
No Acknowledge.
Figure 29 shows the peak I DD supply current during an EEPORM
page erase operation. Decoupling capacitors of 10 μF and 100
nF are recommended on V DD .
Figure 29. EEPROM Page Erase Peak I DD Current
SMBus Write Operations
Page No.
1
2
3
EEPROM Location
8000h to 801Fh
8020h to 803Fh
8040h to 8050h
Description
Available FRU
Available FRU
Available FRU
Send Byte
In this operation, the master device sends a single command
byte to a slave device, as follows:
4
5
6
7
8
9
10
11
12
13
14
15
16
8060h to 8070h
8080h to 8090h
80A0h to 80BFh
80C0h to 80DFh
80E0h to 80FFh
8100h to 811Fh
8120h to 813Fh
8140h to 815Fh
8160h to 817Fh
8180h to 819Fh
81A0h to 81BFh
81C0h to 81DFh
81E0h to 81FFh
Available FRU
Available FRU
Available FRU
Available FRU
Available FRU
Configuration Boot Registers
ADI Registers
Available FRU
Available FRU
Available FRU
Available FRU
Available FRU
ADI Registers
1.
2.
3.
4.
5.
6.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
write bit (low).
The addressed slave device asserts ACK on SDA.
The master sends a command code.
The slave asserts ACK on SDA.
The master asserts a stop condition on SDA and the
transaction ends.
Rev. A | Page 36 of 64
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